Semiconductor memories can be classified as volatile (where stored information is lost upon power removal) and non-volatile (where stored information is maintained after power removal, and which can be accurately retrieved after subsequent power-up). Several types of non-volatile semi-conductor memories are known, notably based on MNOS transistors, FAMOS transistors, or FATMOS transistors. A description of prior MNOS and FAMOS memory circuits is given in U.S. Pat. No. 4,132,904. The latter patent, together with U.K. Specification No. 2,000,407 describe and claim FATMOS non-volatile latch memory circuits.
The FATMOS is basically a control gate plus floating gate MOS transistor with a portion of the floating gate lying close to the semiconductor substrate. When the source and drain connections are connected to an appropriate potential (one positive relative to the other) and a suitable potential of a first magnitude applied to the control gate, the transistor conducts. Upon removal of the control gate potential, conduction ceases. If a potential of a second and higher magnitude is applied to the control gate with the drain at zero voltage, the transistor again conducts, but in addition electric charges tunnel between the floating gate and the transistor substrate through the portion of the floating gate closest to the substrate. This charge remains on the floating gate even when the control gate potential is removed and increases the switching threshold of the device. This charge on the floating gate enables the transistor to be employed in a non-volatile memory, as described in U.K. Specification No. 2,00,407. The switching threshold of the FATMOS is returned to its original level by applying between the control gate and drain a potential of approximately the second and higher potential, but of opposite polarity.
In a typical example of an N-channel enhancement-type FATMOS, the area of the floating gate closest to the substrate overlies the drain of the transistors, although this is not essential and the area closest to the substrate can be elsewhere on the transistor. In normal, non-volatile operation of a latch including such a FATMOS device, a voltage of typically +5 to +7 volts is applied to the control gate of the FATMOS. To write non-volatile information into the latch, a voltage of typically +8 to +15 volts is applied to the control gate of the FATMOS. If power is removed from the latch and then subsequently restored, it settles into a logic state dictated by its state during the earlier non-volatile write operation.
Although FATMOS transistors work well when employed in non-volatile memory cells (see U.K. Specification No. 2,000,407) certain configurations of FATMOS transistors can sometimes be unpredictable during reading after the FATMOS's have been placed in their non-volatile written mode (higher threshold state). This unpredictability manifests itself by the FATMOS transistor(s) switching to the wrong state (i.e. a FATMOS with a charge retained on its floating gate being held "off" instead of "on" and vice-versa).
Wrong state switching during reading is particularly noticeable when the shift in the switching threshold of a FATMOS is low, as can occur towards the end of the life of a FATMOS or as a result of normal production variations. The low threshold shift increases the relative effect of other sources of imbalance in the memory cell which may override the effect of the threshold shift and cause the cell to go into the wrong state on reading.
The present invention is concerned with reducing the imbalance in a memory cell due to effects other than those produced by putting the FATMOS devices into their non-volatile modes, so as to improve the reliability of the cell when the threshold shifts are low.